module top;
system_clock #400 clock1(a);
system_clock #200 clock1(b);
system_clock #100 clock1(c);
system_clock #50 clock1(d);
number n1(e,a,b,c,d);
endmodule

module number(e,a,b,c,d);
input a,b,c,d;
output e;
wire a1,b1,c1,d1,w1,w2,w3,w4,w5;
not(a1,a);
not(b1,b);
not(c1,c);
not(d1,d);
and(w1,a1,b,c1);
and(w2,a,b,c);
and(w3,a,b1,c,d);
and(w4,a,b1,c1,d1);
and(w5,a1,b1,c,d1);

or(e,w1,w2,w3,w4,w5);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule
module top;
system_clock #400 clock1(a);
system_clock #200 clock1(b);
system_clock #100 clock1(c);
system_clock #50 clock1(d);
number n1(e,a,b,c,d);
endmodule

module number(e,a,b,c,d);
input a,b,c,d;
output e;
wire a1,b1,c1,d1,w1,w2,w3,w4,w5;
not(a1,a);
not(b1,b);
not(c1,c);
not(d1,d);
and(w1,a1,b,c1);
and(w2,a,b,c);
and(w3,a,b1,c,d);
and(w4,a,b1,c1,d1);
and(w5,a1,b1,c,d1);

or(e,w1,w2,w3,w4,w5);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule

2位元比較器含時脈周期

wire A_lt_B,A_gt_B,A_eq_B,A1,A0,B1,B0;

system_clock #100 clock_1(A1);
system_clock #200 clock_2(A0);
system_clock #400 clock_3(B1);
system_clock #800 clock_4(B0);

compare_2a X1(A_lt_B,A_gt_B,A_eq_B,A1,A0,B1,B0);

endmodule

module compare_2a(A_lt_B,A_gt_B,A_eq_B,A1,A0,B1,B0);
input A1,A0,B1,B0;
output A_lt_B,A_gt_B,A_eq_B;
wire A_lt_B,A_gt_B,A_eq_B;
assign A_lt_B=(~A1)&B1(~A1)&(~A0)&B0(~A0)&B1&B0;
assign A_gt_B=A1&(~B1)A0&(~A0)&(~B0)(~A0)&B1&B0;
assign A_eq_B=(~A1)&(~A0)&(~B1)&(~B0)(~A1)&A0&(~B1)&B0A1&A0&B1&B0A1&(~A0)&B1&(~B0);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;
always begin#(PERIOD/2) clk=~clk ;#(PERIOD-PERIOD/2) clk=~clk ;end
mailto:always@%20(posedge clk)if($time>10000) #(PERIOD-1) $stop;
endmodule

比較器2

module compare_2a(A_lt_B,A_gt_B,A_eq_B,A1,A0,B1,B0);
input A1,A0,B1,B0;
output A_lt_B,A_gt_B,A_eq_B;
wire A_lt_B,A_gt_B,A_eq_B;
assign A_lt_B=(~A1)&B1(~A1)&(~A0)&B0(~A0)&B1&B0;
assign A_gt_B=A1&(~B1)A0&(~A0)&(~B0)(~A0)&B1&B0;
assign A_eq_B=(~A1)&(~A0)&(~B1)&(~B0)(~A1)&A0&(~B1)&B0A1&A0&B1&B0A1&(~A0)&B1&(~B0);
endmodule

10/5 work

module mux;
integer ia,ib,isel;
reg a,b,sel;
wire out;

not I5(sel_n,sel);

and I6(sel_a,a,sel);
and I7(sel_b,sel_n,b);

or I4(out,sel_a,sel_b);

initial
begin
for(ia=0;ia<=1;ia=ia+1)
begin a=ia;
for(ib=0;ib<=1;ib=ib+1)
begin b=ib;
for(isel=0;isel<=1;isel=isel+1)
begin sel=isel;

#10;
end
end
end
end
endmodule

module and4_rtl(y_out,x_in1,x_in2,x_in3,x_in4);

input x_in1,x_in2,x_in3,x_in4;

output y_out;

assign y_out=x_in1&x_in2&x_in3&x_in4;

endmodule

module and4_rtl(y_out,x_in);

input [ 3:0] x_in;

out y_out;

assign y_out=&x_in;

endmodule

硬體描述語言 C語言與電路合起來的方式

module part1;

integer ia,ib;

reg a,b;

wire c;

xor x1(c,a,b);

initial

begin

for(ia=0;ia<=1ia++)

begin

a=ia;

for(ib=0;ib<=1;ib++)

begin

b=ib;
#10 $display("a=5d b=%d c=%d",a,b,c);

end

end

endendmodule

VIG硬體語言 AND 邏輯閘 n.1 work

module top;

wire a,b;

reg c ;

system_clock # 100 clock1(a);

system_clock # 50 clock2(b);

always

#1 c=a&b;

endmodule

module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial

clk=0;

always

begin

#(PERIOD/2)clk=~clk ;

#(PERIOD-PERIOD/2)clk=~clk;

endalways@(posedge clk)

if($time>1000)#(PERIOD-1)$stop;

endmodule