10/5 work

module mux;
integer ia,ib,isel;
reg a,b,sel;
wire out;

not I5(sel_n,sel);

and I6(sel_a,a,sel);
and I7(sel_b,sel_n,b);

or I4(out,sel_a,sel_b);

initial
begin
for(ia=0;ia<=1;ia=ia+1)
begin a=ia;
for(ib=0;ib<=1;ib=ib+1)
begin b=ib;
for(isel=0;isel<=1;isel=isel+1)
begin sel=isel;

#10;
end
end
end
end
endmodule